1. Field of the Invention
The present invention relates to a data processing apparatus and method for performing floating point addition, and in particular to a data processing apparatus and method for adding first and second n-bit significands of first and second floating point operands to produce an n-bit result.
2. Description of the Prior Art
A floating point number can be expressed as follows:±1.x*2y
where: x=fraction                1.x=significand (also known as the mantissa)        y=exponent        
Floating point addition can take two forms, namely like-signed addition (LSA) or unlike-signed addition (USA). An LSA operation is performed if two floating point operands of the same sign are to be added, or if two floating point operands of different signs are to be subtracted. Similarly, a USA operation is to be performed if two floating point operands of different sign are to be added, or if two floating point operands of the same sign are to be subtracted. When referring in the present application to the addition of floating point operands and the addition of the n-bit significands of such operands, this should be taken as collectively referring to LSA or USA computations, and accordingly it will be appreciated that such a term covers both addition and subtraction processes.
When adding the n-bit significands of two floating point operands in order to produce an n-bit result, the following steps need to be performed:    1. A determination is made as to which of the two floating point operands is the largest.    2. The n-bit significand of the smaller operand is then aligned with the n-bit significand of the larger operand.    3. In the event of a USA operation, the smaller operand is inverted and a carry-in bit to subsequent adder logic is set. For an LSA operation, no such inversion is required, and the carry-in bit is not set.    4. The two significand values, manipulated as described above, are then added to produce a non-rounded sum.    5. The non-rounded sum is then normalized (shifted so that it has the form 1.x). The exponent is adjusted accordingly.    6. The bits of the non-rounded sum to the right of the least significant result bit (the result requires only the n most significant bits) are then evaluated to determine whether rounding is appropriate.    7. Then, a rounding increment is added to the significant bits of the result dependent on the rounding evaluation performed in step 6 above.    8. The rounded sum is then normalized (shifted so that it has the form 1.x). The exponent is adjusted accordingly.
The above series of steps are inherently serial, but can be parallelised at several points. In accordance with one known prior art technique, the significands were treated as n-bit integers, and the addition circuitry was arranged such that two additions were performed in parallel, one using the input significands to generate a value “sum”, and one adding a predetermined increment of +2 to the input significands to produce a value “sum+2”, with the rounding evaluation also being performed in parallel. All of the possible results could then be derived from either the sum or “sum+2” values. However, the introduction of the increment value of +2 required the addition of an initial level of full adder logic to be introduced before the level of carry propagate adders used to produce the result “sum+2”, which has an adverse impact on processing speed.
U.S. Pat. No. 6,366,942-B1 describes a technique for rounding floating point results in a digital processing system. The apparatus accepts two floating point numbers as operands in order to perform addition, and includes a rounding adder circuit which can accept the operands and a rounding increment bit at various bit positions. The circuit uses full adders at required bit positions to accommodate a bit from each operand and the rounding bit. Since the proper position in which the rounding bit should be injected into the addition may be unknown at the start, respective low and high increment bit addition circuits are provided to compute a result for both the low and a high increment rounding bit condition. The final result is selected based upon the most significant bit of the low increment rounding bit result. The low and high increment bit addition circuits can share a high order bit addition circuit for those high order bits where a rounding increment is not required, with this single high order bit addition circuit including half adders coupled in sequence, with one half adder per high order bit position of the first and second operands.
Hence, it can be seen that U.S. Pat. No. 6,366,942-B1 teaches a technique which enables the rounding process to be performed before the final sum result is produced, but in order to do this requires the use of a level of fall adders (i.e. adders that take three input bits and produce at their output a carry and a sum bit) and half adders before the adder logic used to produce the final sum.
Full adders typically take twice as long to generate output carry and sum bits as do half adders. As there is a general desire to perform data processing operations more and more quickly, this tends to lead to a reduction in the clock period (also referred to herein as the cycle time) within the data processing apparatus. As the cycle time reduces, the delays incurred through the use of the extra level of the full adders and half adders (and especially the delay incurred by the full adders) described above are likely to become unacceptable.